1. Technical Field
The present invention relates to a method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor apparatus and a photomask. In particular, the invention relates to a technique for forming a SOI (Silicon on Insulator) structure on a semiconductor substrate.
2. Related Art
A field effect type transistor formed on a Silicon On Insulator (SOI) substrate has attracted attention for the usefulness because elements can be separated easily, it is latchup free, and it has a small source/drain junction capacity for embodiment. A complete depletion type SOI transistor in particular, which consumes a low power and can be operated with a high speed and can be easily driven with a low voltage, has been actively researched in order to operate the SOI transistor with a complete depletion mode.
SOI substrates are produced using a technique such as a Separation by Implanted Oxygen (SIMOX) substrate and a laminated substrate. However, these techniques use special manufacture processes and thus cannot use a general CMOS process
Due to this reason, Separation by Bonding Silicon Islands (SBSI), which is a method for manufacturing a SOI structure out of a common bulk silicon wafer by a general CMOS process, has been known (see the following embodiment for embodiment). Hereinafter, a method for manufacturing a semiconductor apparatus according to this SBSI method (conventional embodiment) will be described.
FIG. 10A to FIG. 16C illustrate a method for manufacturing a semiconductor substrate according to a conventional embodiment. In particular, FIG. 10A, FIG. 11A, FIG. 12A, FIG. 13A, FIG. 14A, FIG. 15A, and FIG. 16A are a top view illustrating a method for manufacturing a semiconductor substrate according to a conventional embodiment, respectively. FIG. 10B, FIG. 11B, FIG. 12B, FIG. 13B, FIG. 14B, FIG. 15B, and FIG. 16B are a cross-sectional view illustrating FIG. 10A, FIG. 11A, FIG. 12A, FIG. 13A, FIG. 14A, FIG. 15A, and FIG. 16A cut at a line a-a′. FIG. 12C, FIG. 13C, FIG. 14C, FIG. 15C, and FIG. 16C are a cross-sectional view illustrating FIG. 12A, FIG. 13A, FIG. 14A, FIG. 15A, and FIG. 16A cut at a line b-b′.
As shown in FIGS. 10A and 10B, a semiconductor substrate in a conventional embodiment is manufactured by firstly forming a SiGe layer 103 on a Si substrate 101 as a bulk silicon wafer to form a Si layer (SOI layer) 105 on the SiGe layer 103. The SiGe layer 103 and the Si layer 105 are formed by an epitaxial growth, respectively. Next, trenches h′ for a supporting body are formed in the Si layer 105 and the SiGe layer 103 in the vicinity of element regions. Specifically, trench formation regions are opened as shown in FIGS. 10A and 10B and resist patterns 106 for covering regions other than them are formed.
Next, the Si layer 105 and the SiGe layer 103 are sequentially etched by using this resist pattern 106 as a mask to expose a surface of the Si substrate 101 under the resist pattern 106. As a result, the trench h′ is formed. Hereinafter, a region in which this trench h′ is formed will be called as “the first pattern”.
Next, the resist patterns 106 are removed. Then, as shown in FIGS. 11A and 11B, a method such as CVD is used to form a supporting body (e.g., SiO2 film) 107 over the entire upper part of the Si substrate 101. Next, as shown in FIGS. 12A to 12C, the supporting body 107 has thereon a resist pattern 111 that covers a wide region from a region in which the SOI structure is formed to the trenches h′.
Then, as shown in FIGS. 13A to 13C, the supporting body 107, the Si layer 105, and the SiGe layer 103 are sequentially etched by using this resist pattern 111 as a mask. These etchings are performed by using an anisotropic dry etching apparatus. As a result, an aperture plane that exposes a part of a side face of the SiGe layer 103 and a part of a side face of the Si layer 105 (end section) is formed in the supporting body 107. This etching leaves the Si layer 105 and the SiGe layer 103 only on the Si substrate 101 of the element region and removes the Si layer 105 and the SiGe layer 103 from the Si substrate 101 on regions other than the element region. Hereinafter, a region covered by the patterned supporting body 101 will be called as “the second pattern”.
Next, the SiGe layer 103 and the Si layer 105 have a contact with etching solution such as mixture of fluoric acid and nitric acid via the aperture plane formed in supporting body 107 to etch and remove only the SiGe layer 103. As a result, a hollow section 121 is formed as shown in FIGS. 14A to 14C between the Si substrate 101 and the Si layer 105. Next, the Si substrate 101 is subjected to thermal oxidation in which oxidizing species such as O2 reaches not only the surface of the substrate 101 exposed under the supporting body 107 but also the hollow section 121 via the aperture plane. This forms, as shown in FIGS. 15A to 15C, a SiO2 film (BOX layer) 131 in the hollow section.
Next, as shown in FIGS. 16A to 16C, a method such as CVD is used to firm a SiO2 film 133 for an element isolation over the entire upper face of the Si substrate 101. Then, CMP is used to planarize the entire upper face of the Si substrate 101 to remove the SiO2 film 133 and the supporting body 107 from the upper part of the Si layer 105. As a result, a structure is completed in the Si substrate 101 in which the upper face of the Si layer 105 is exposed and the Si layer 105 is element-divided by an insulation film (i.e., SOI structure).
An embodiment of related art is “Separation by Bonding Si Islands (SBSI) for LSI Applications” (T, Sakai et al., Second International SiGe Technology and Device Meeting Abstract, pp. 230-231, May (2004)).
By the way, the method for manufacturing a semiconductor substrate according to the above conventional embodiment provides a structure as shown in FIG. 12(A) in which the first patterns are formed at opposing sides (e.g., left and right sides) of the second pattern having a rectangular shape when seen from the top and in which the first pattern is not formed at the other pair of sides (e.g., upper and lower sides).
When the SOI structure is formed with the positional relation of the first and second patterns as described above, the Si layer 105 and the SiO2 film 131 are pressed by the supporting body only at one pair of sides (e.g., left and right sides) for embodiment and are not pressed by the other pair of sides (e.g., upper and lower sides). Due to this, some oxidation conditions or heating conditions may cause an excessive stress to the supporting body. This may cause a risk where the Si layer 105 and the SiO2 film 131 are bent as shown in FIG. 17 to have a curved cross section to cause a space S at the center of an active region.
As described above, the space S at the center of the active region may suppress heat generated at a transistor from escaping to the Si substrate 101, thus deteriorating the transistor characteristic.